1. Field of the Invention
The present invention relates to a method and apparatus for providing salphasic (characterized by discontinuous progression or abrupt jumps in the advancement of phase with distance) distribution of timing signals for synchronizing the operations of multiple entities, typically composing a system, which are physically separated by distances that would normally cause significant propagation-delay-induced phase shifts. More particularly, the present invention relates to a method for exploiting a salphasic behavior arising from fundamental wave propagation properties to minimize phase differences of timing signals resulting from unequal signal path lengths between a timing signal source and various entities to be synchronized. Yet more particularly, the present invention pertains to application of said salphasic distribution of electrical clock signals to synchronous electronic digital systems.
2. Description of Prior Art
Synchronous system design methodology is well developed and widely used for electronic digital systems. This methodology typically employs rectangular-wave clock and data signals propagated over conductors between communicating modules. To provide clear clock communication, the clock receivers in these modules must be arranged and coordinated with the clock distribution conductors to minimize reflections of the clock signal on these conductors. Therefore, under this design methodology, an important, goal is to impedance match the loads of the clock distribution conductors to eliminate signal reflections.
However, the time delays inherent in the propagation of signals along interconnecting conductors limit the design of synchronous systems. This design limitation becomes increasingly significant as system path lengths grow larger in comparison to the wavelength of the system clock signal. For example, designers need not be too concerned about clock skew (differences in clock phase between various system locations) in systems having relatively small path lengths because clock signals appear nearly in the same phase at all system locations. But for systems having relatively long path lengths, designers must consider clock skew because the phase shifts incurred by the propagation delays along these paths can become an appreciable fraction of the clock cycle and thus may disrupt system operation.
To deal with delay problems, some synchronous system organizations constrain path lengths between communicating modules. However, global clock signals must still propagate across the entire system of modules in a manner that preserves the correct sequence of events throughout the system as discussed in A. L. Fisher and H. T. Kung, "Synchronizing Large VLSI Processor Arrays", IEEE T-C, vol. C-34, no. 8, August 1985. Accordingly, the time delay between communicating modules must not exceed acceptable values, or correct sequencing will be lost. Thus, for large systems containing many modules, clock signal considerations remain important. Moreover, the trend is towards higher clock speeds and more massive systems, both of which increase the need for designers to account properly for these propagation delay limitations.
There are numerous approaches to reduce the variation in clock delays (or the effects thereof) experienced by the system modules, as discussed in K. D. Wagner, "Clock System Design", IEEE Design and Test of Computers, October 1988. One approach is to select a clocking discipline appropriate to the implementing technology to maximize robustness to skew as discussed in S. H. Unger and C-J. Tan, "Clocking Schemes for High-Speed Digital Systems", IEEE T-C, vol. C-35, no. 10, October 1986.
Other approaches tune distribution network conductor lengths and/or amplifier delays to minimize clock skew across the synchronized modules of the system, as discussed for example in Wagner (op.cit.); E.G. Friedman and S. Powell, "Design and Analysis of a Hierarchical Clock Distribution System for Synchronous Standard Cell/Macrocell VLSI", IEEE J-SC, vol. SC-21, no. 2, April, 1986; K. D. Wagner and E. J. McClusky, "Tuning, clock distribution, and communication in VLSI high speed chips", Stanford University CRC Technical Report 84-5, June 1984.
These well proven approaches, however, impose their own constraints on the system design, and in particular they increase the complexity of the design process.
A fundamentally different approach is to abandon altogether the synchronous design methodology in favor of self-timed and asynchronous delay-insensitive disciplines as discussed in C. L. Seitz, "Self-timed VLSI Systems", Proc. Caltech Conference on VLSI, January 1979; C. E. Molnar, "Introduction to Asynchronous Systems", Proc. New Frontiers in Computer Architecture Conference, March 1986; I. E. Sutherland, "Micropipelines", Communications of the ACM, vol. 32 no. 6, June 1989.
These disciplines appear to afford scalability to any system size and speed at the expense of additional hardware. This increases the design effort and ultimate cost of constructing a system and may not be justified for some system speeds and sizes if synchronous alternatives are feasible. Although asynchronous design methodology may some day become the mainstream methodology of choice, it is substantially different from synchronous methodology, and is neither widely understood nor practiced today.
Although each of these approaches (barring the asynchronous technique) effectively reduces the effects of clock propagation delay skew in certain synchronous designs, all fail to provide a simple, uniform design methodology to minimize the actual clock skew in large, high speed, synchronous systems of arbitrary interconnect topology without explicitly addressing the geometric details of the interconnections.